Verilog syntax highlighting

[GoAWest]

I just moved UE12 to a new PC and had to dig out, copy or reconfig some settings. This included the wordfile, including a Verilog syntax highlight template I created a while ago. I first popped onto this forum to see if I could find a newer/better one but didn't see one (VHDL was the closest). However, a websearch found the one below (Verilog syntax highlighting for UltraEdit, Icarus Verilog for Windows, http://bleyer.org/icarus/) which was more complete than the one I had created myself, so I'm posting it here for others.

Note: tab in the line starting with /Delimiters = must be replaced with a tab character after copying the language definition to a text file in UltraEdit.

----------------------------------------------

/L20"Verilog 1364-2001" Line Comment = // Block Comment On = /* Block Comment Off = */ Block Comment On Alt = (* Block Comment Off Alt = *) String Chars = " File Extensions = V VL VMD
/Delimiters = ~!@%^&*()-+=|\/{}[]:;"<> ,tab#
/Function String = "%[ ^t]++^(config[ ^t^p]+[a-zA-Z0-9_]+^)"
/Function String 1 = "%[ ^t]++^(module[ ^t^p]+[a-zA-Z0-9_]+^)[ ^t^p]++[(;#]"
/Function String 2 = "%[ ^t]++^(task[ ^t^p]+[~(;]+^)[ ^t^p]++[(;#]"
/Function String 3 = "%[ ^t]++^(function[ ^t^p]+[~(;]+^)[ ^t^p]++[(;#]"
/Function String 4 = "%[ ^t]++^(primitive[ ^t^p]+[~(;]+^)[ ^t^p]++[(;#]"
/Function String 5 = "begin[ ^t^p]++^(:[ ^t^p]++[a-zA-Z0-9_]+^)"
/Indent Strings = "begin" "case" "fork" "specify" "table" "config"
/Unindent Strings = "end" "endcase" "join" "endspecify" "endtable" "endconfig"
/Open Fold Strings = "module" "task" "function" "generate" "primitive" "begin" "case" "fork" "specify" "table" "config" "`ifdef"
/Close Fold Strings = "endmodule" "endtask" "endfunction" "endgenerate" "endprimitive" "end" "endcase" "join" "endspecify" "endtable" "endconfig" "`endif"
/C1"Keywords"
always and assign automatic
begin buf bufif0 bufif1
case casex casez cell cmos config
deassign default defparam design disable
edge else end endcase endconfig endmodule endfunction endgenerate endprimitive endspecify endtable endtask event
for force forever fork function
generate genvar
highz0 highz1
if ifnone initial inout input instance integer
join
large liblist library localparam
macromodule medium module
nand negedge nmos none nor noshowcancelled not notif0 notif1
or output
parameter pulsestyle_onevent pulsestyle_ondetect pmos posedge primitive pull0 pull1 pullup pulldown
real realtime reg release repeat rcmos rnmos rpmos rtran rtranif0 rtanif1
scalared showcancelled signed small specify specparam strength strong0 strong1 supply0 supply1
table task time tran tranif0 tranif1 tri tri1 tri0 triand trior trireg
use
vectored
wait wand weak0 weak1 while wire wor
xnor xor
/C2"System"
** .
** 'b 'B 'o 'O 'd 'D 'h 'H 'sb 'sB 'so 'sO 'sd 'sD 'sh 'sH 'Sb 'SB 'So 'SO 'Sd 'SD 'Sh 'SH
** $
$async$and$array $async$and$plane $async$nand$array $async$nand$plane $async$nor$array $async$nor$plane $async$or$array $async$or$plane
$bitstoreal
$countdrivers
$display $displayb $displayh $displayo
$dist_chi_square $dist_erlang $dist_exponential $dist_normal $dist_poisson $dist_t $dist_uniform
$dumpall $dumpfile $dumpflush $dumplimit $dumpoff $dumpon $dumpportsall $dumpportsflush $dumpportslimit $dumpportsoff $dumpportson $dumpvars
$fclose $fdisplayh $fdisplay $fdisplayf $fdisplayb $ferror $fflush $fgetc $fgets $finish $fmonitorb $fmonitor $fmonitorf $fmonitorh $fopen $fread $fscanf $fseek $fsscanf $fstrobe $fstrobebb $fstrobef $fstrobeh $ftel $fullskew $fwriteb $fwritef $fwriteh $fwrite
$getpattern
$history $hold
$incsave $input $itor
$key
$list $log
$monitorb $monitorh $monitoroff $monitoron $monitor $monitoro
$nochange $nokey $nolog
$period $printtimescale
$q_add $q_exam $q_full $q_initialize $q_remove
$random $readmemb $readmemh $realtime $realtobits $recovery $recrem $removal $reset_count $reset $reset_value $restart $rewind $rtoi
$save $scale $scope $sdf_annotate $setup $setuphold $sformat $showscopes $showvariables $showvars $signed $skew $sreadmemb $sreadmemh $stime $stop $strobeb $strobe $strobeh $strobeo $swriteb $swriteh $swriteo $swrite $sync$and$array $sync$and$plane $sync$nand$array $sync$nand$plane $sync$nor$array $sync$nor$plane $sync$or$array $sync$or$plane
$test$plusargs $time $timeformat $timeskew
$ungetc $unsigned
$value$plusargs
$width $writeb $writeh $write $writeo
/C3"Operators"
!
%
&
*
+
,
-
// /
:
;
<
=
>
?
@
^
{
|
}
~
/C4"Directives"
** `
`accelerate `autoexepand_vectornets
`celldefine
`default_nettype `define `default_decay_time `default_trireg_strength `delay_mode_distributed `delay_mode_path `delay_mode_unit `delay_mode_zero
`else `elsif `endcelldefine `endif `endprotect `endprotected `expand_vectornets
`file
`ifdef `ifndef `include
`line
`noaccelerate `noexpand_vectornets `noremove_gatenames `noremove_netnames `nounconnected_drive
`protect `protected
`remove_gatenames `remove_netnames `resetall
`timescale
`unconnected_drive `undef `uselib
/C5"DelaysParametersEscaped"
#
** \

[Mofi]

I have corrected in your post the list of operators. The operator characters are also delimiter characters. So single characters must be specified for highlighting the operators independent on the combination they are used for. And I added the special info about the tab character in the list of delimiters.

I'm only wondering about all those words in /C2 starting with $. In the same color group there is also the substring definition ** $ which means highlight all words starting with a $. So why are additionally all those words starting with $ also listed. I think, they are completely useless as long as ** $ exists in the same color group.

Can you verify that by deleting all the words in /C2 starting with $ and look, if they are still highlighted with color 2?

[dmk11]

Mine is similar to the above, but I added the following:

/Open Brace Strings = "{" "(" "["
/Close Brace Strings = "}" ")" "]"


useful for matching braces.
Is there an UltraEdit keystroke that will bring me to the matching brace? (like % in vi).

and the Verilog2001 file on this website has a better list of operators: http://www.ultraedit.com/files/wf/verilog2001.uew

One problem I noticed with this definition is that it doesn't support the new System Verilog syntax.
ex: always @(*)

[Mofi]

Is there an UltraEdit keystroke that will bring me to the matching brace?

There is the command Search - Match Brace. You can assign any hotkey to it in the keyboard configuration dialog, command SearchMatchBrace. And there is an option in the syntax highlighting configuration dialog named Enable Auto Brace Matching. Details about the command and the configuration option can be found in help of UltraEdit.

And the Verilog2001 file on this website has a better list of operators.

I have already explained in my first post why I have corrected the list of operators to what you can see now in the first post. All operators are also delimiter characters = separators for words. So the operators list in the Verilog2001 file is too much, because for example >= is interpreted by the syntax highlighting engine as single character word > and single character word =. So it is enough and really correct only to specify the single character operators independent in which combination they are used for in the Verilog file.

One problem I noticed with this definition is that it doesn't support the new System Verilog syntax.
ex: always @(*)

I don't know the Verilog syntax. Can you explain it more detailed. Maybe I can find a solution.

[toddm]

always @(*)

I love that feature. No more forgetting to put signals in my sensitivity list.

[dmk11]

I don't know the Verilog syntax. Can you explain it more detailed. Maybe I can find a solution.

In regular verilog, you need to specify individual signals used in an always block.
Ex:
always @(sig1 or sig2 or sig3)
OR
always @(sig1, sig2, sig3)

In addition to the above, System Verilog also support
always @(*)

it'll automatically take all the signals used in the always block and assumed it's in the list.

The current syntax definition think of it as the start of a block comment.