Syntax highlighting wordfile for VHDL

[illico]

See below my VHDL language syntax highlighting.
Uses the Function list features.
Uses the Code folding features.
I put it here, just for information and any suggestion.

The character between the round brackets on line starting with /Delimiters = is a tab character and not a sequence of space characters!

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/L20"VHDL" Nocase Line Comment = -- String Chars = " File Extensions = VHD VHO VHDL TVHD
/Delimiters = ; (   )'<>=:+-/*|&
/Function String = "^(^{signal^}^{constant^}[a-z0-9 ]*:[a-z0-9 ]*^);"
/Function String 1 = "component[a-z0-9 ]*is"
/Function String 2 = "%^(*[a-z0-9 ]*:[a-z0-9 ]*^p[a-z0-9 ]* map[ ]++^)"
/Function String 3 = "%^(architecture [a-z0-9 ]* of [a-z0-9 ]*^) is"
/Function String 4 = "%[a-z0-9 ]*:[ ]++process"
/Function String 5 = "^{function^}^{procedure^}[a-z0-9 ]*"
/Indent Strings = "(" "begin" "then" "loop"
/Unindent Strings = ")" "else" "elsif" "end if"
/Open Fold Strings = "(" "begin" "if" "loop"
/Close Fold Strings = ")" "end process" "end if" "end loop"
/Open Brace Strings = "("
/Close Brace Strings = ")"
/C1"VHDL reserved words"
abs access after alias all and architecture array assert attribute
begin block body buffer bus
case component configuration constant
disconnect downto
else elsif end entity exit
false file for function
generate generic group guarded
if impure in inertial inout is
label library linkage literal loop
map mod
nand new next nor not null
of on open or others out
package port postponed procedure process pure
range record register reject rem report return rol ror
select severity shared signal sla sll sra srl subtype
then to transport true type
unaffected units until use
variable
wait when while with
xnor xor
/C2"VHDL attributes"
active ascending
base
delayed driving driving_value
event
falling_edge
high
image instance_name
last_active last_event last_value left leftof length low
path_name pos pred
quiet
reverse_range right rightof rising_edge
simple_name stable succ
transaction
val value
/C3"VHDL types"
bit bit_vector boolean
character
integer
line
natural
positive
real
signed std_logic std_logic_vector string
text time
unsigned
/C4"VHDL Procedures"
endfile endline
file_close file_open
read readline
write writeline
/C5"VHDL Convertion"
to_integer to_unsigned

[Mofi]

I don't have any experience with VHDL, but I have a lot with creating syntax highlighting definitions. So here are my suggestions:

Because function strings are always searched not case sensitive, it is not necessary to define [a-zA-Z0-9 ], the expression [a-z0-9 ] is enough (and applied to wordfile posted above like other small corrections).

Is [a-z0-9 ]* really the correct definition?
This means find a string starting with a letter, number or space followed by any amount of any character to next specified search criteria.
[a-z0-9 ]+ would find a string with at least 1 character, but only letters, numbers and spaces are valid string characters.

Example string: Hello world!! Function:

Search string [a-z0-9 ]*: finds the complete string, [a-z0-9 ]+: only " Function:".

[palou]

Hi illico,

mine is really similar to yours, I think we started from the same
One small difference is in the Delimiters where you don't have the ',' (perhaps it's intentional). I made the following color definition for hexa / binary strings (thank's Mofi's suggestion):

Code: Select all

/C3"VHDL strings"
** X" B"

I have written also a few macro to auto complete structures like block, process, case and if. If your are interested I can give you the macro source code.

Just a question: I saw you defined the Open/Close Fold Strings. Did you use UE v11? Is the code folding correctly working? It's a major feature for that make me upgrading to v11.

Salutations de Genève.
Alain

[illico]

Did you use UE v11? Is the code folding correctly working?

Yes, I'm testing UE version 11.00+ and code folding.

The code folding works fine for "component" declaration "port map" and "process".
But there are somes rules to respect ( process labels...) :

Code: Select all

  component component_name is
  port (
      signal_a : in std_logic; --
      signal_b : in std_logic; --
      signal_c : out std_logic --
    );
  end component;

  u_component_name : component_name
    port map (
      signal_a       => signal_a      ,
      signal_b       => signal_b      ,
      signal_c       => signal_c
    );

  p_signal_a : process ( clk, rst_n )
  begin
    if ( rst_n = '0' ) then
      signal_a_i <= '1';
    elsif rising_edge(clk) then
      signal_a_i <= signal_a;
    end if;
  end process;

The code folding result:

Code: Select all

  component component_name is
  port
+ (
    );
  end component;

  u_component_name : component_name
+  port map (
    );

  p_signal_a : process ( clk, rst_n )
+  begin
  end process;

[phireboy]

Hi!
Your code has proven very helpful, but there are a few things that I am unable to do...
How do I command UE to recognize and automatically fill in library names?

USE ieee.STD_LOGIC_1164.all;
USE ieee.STD_LOGIC_unsigned.all;

and so on?

thanks

[Mofi]

Create a new color group (/C6, /C7 or /C8) with the library names (sorted correct) or use an auto complete file for your VHDL files - see Configuration - Editor - Word Wrap / Tab Settings. Use forum search and help of UltraEdit for more infos about auto completion.

[vhdluser]

Great file!
Works for me, except...
1. It doesn't like TABs before keywords, and a few other instances
Yes I could stop using TABs, but I like'em.
2. When the editor gets switched over to "column" mode, it changes font to smaller and much less readable. Squinting required. Can anything be done about that.
I will appreciate any help / thoughts on above.

[Mofi]

1. It doesn't like TABs before keywords, and a few other instances. Yes, I could stop using TABs but I like'em.

In HTML a tab is interpreted always as a single space character - HTML standard. In preformatted text a tab is displayed as a sequence of spaces.

In the line /Delimiters = ; (tab)'<>=:+-/*|& the multiple spaces in your wordfile after copying from above must be replaced by a tab. Simply select the spaces between the round brackets and press the tab key. Save the wordfile and your problems with the tabs are solved.

2. When the editor gets switched over to "column" mode, it changes font to smaller and much less readable. Squinting required.

In menu View click on Set HEX/Column Mode Font and select the same font size as you have specified in View - Set Font. The font for HEX/Column Mode must be a non proportional font like Courier New.

[vhdluser]

It worked. Thanks a lot.

But I run into new issues.
VHDL has the following 3 frequently used nesting constructs that share keywords:

Code: Select all

if blahblahblah then
    blahblahblah
end if
if blahblahblah generate
    blahblahblah
end generate
for blahblahblah generate
    blahblahblah
end generate

Has anyone attempted to make the fold/unfold feature work with all three?
I tried modifying the above template to read:

/Open Fold Strings = "(" "begin" "if" "loop" "case"
/Close Fold Strings = ")" "end process" "end[ tab]^{if^}^{generate^}" "end loop""end case"

with the items in square brackets being a space and a tab.
It is not working. It breaks a great deal altogether.
Note that I've earlier added one more folding construct: "case blahblah end case" and that's working fine.

Does this string definition in this context follow regular expressions? The documentation is not clear.

Anyone could shed some light / ideas?

[Mofi]

For regular expression usage in syntax highlighting word files see Close fold with end of text.

I don't know VHDL, but following worked perfect on your small example:

/Open Fold Strings = "(" "begin" "if" "loop" "case" "for"
/Close Fold Strings = ")" "end process" "end if" "end loop" "end case" "end generate"

Maybe you post enclosed in [code][/code] a more complex example - collapsed and not collapsed.

[vhdluser]

There.. I finally got it. Same problem as before: the tabs.
Now my line reads:

Code: Select all

/Close Fold Strings = ")" "end process" "end if" "end loop" "end case" "end generate" "end   process" "end   if" "end   loop" "end   case" "end   generate"

where the second repeated strings have tabs instead of spaces.

It is unfortunate that the regular expression usage is so restricted.

Thanks again, Mofi. I would have given up without your post.

[Dawk]

/Indent Strings = "(" "begin" "then" "loop"
/Unindent Strings = ")" "else" "elsif" "end if"
/Open Fold Strings = "(" "begin" "if" "loop"
/Close Fold Strings = ")" "end process" "end if" "end loop"

Hmm, wouldn't it be easier to just have
/Close Fold Strings = "(" "end"
- "end" would then match all 3 of the above...

Also, I like to have "else" in both /Indent and /Unindent in order to have the "else" line unindented and then the next line indented again. The same would probably apply to "elsif".

Similarly, I have "else" in both /Open Fold and /Close Fold, thus enabling me to fold the first and second parts of

Code: Select all

if () then
...
else
...
end if

separately. This does not break the ability to fold a simple

Code: Select all

if () then
...
end if

(Not completely sure about the syntax of VHDL, but you probably get the idea...)

/Dawk

[vhdluser]

Thanks for your interest, Dawk.
I've tried it, thinking "hey! I've been overcomplicating this thing all along.." and here is what I got:

Code: Select all

if condition1 then -- (+) looks beyond line 10 "end if" for a matching end
   if condition2 then -- (+) perfectly working fold
      line_1_start <= '1';
   else
      line_1_start <= '0';
   end if; -- (+) produces unnecessary fold anchor
else
   line_1_start <= '0';
end if; -- (+) produces yet another unnecessary fold anchor

It seems like the "if"s in "end if", being defined as starting strings, sabotage the whole operation unless they are included in the termination string.
None of this is a bug, it works as advertized. What is less obvious (or stated anywhere for that matter) is any priority order of string matching and resolution logic when overlapping string matches are possible. Sadly, these details can show up when trying to highlight VHDL.

Cheers - VHDL'er

[wimille]

Hello everyone,

I get the VHDL wordfile from IDM website, and I have added some features found on this forum, but not really about the function list.

This is what I want to have in the function list (well, I don't know it's possible or not):

Code: Select all

Procedures [group]
   procedure_1 (parameter)

Process [group]
  name_process ( parameter)

For procedures I use this regexp :

Code: Select all

%[ ^t^b]+procedure[ ^t]+?+

It found all my procedures, but it displays also the keyword procedures which I don't want.

For process, the problem is almost the same.
The regexp I use is:

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%[ ^t^b0-9a-z_:]++process[ ^t0-9a-z_]+

But it displays also the line with 'end process' which I don't want.

If anyone have any idea.
Thank you.

[Mofi]

What you want is most probably possible. There are 2 wordfiles for VHDL on the extras download page: vhdl.uew and vhdl93.uew. I assume you use the first one which is newer.

My problem on helping you is that I'm an expert for UltraEdit regular expression strings, but I'm not familiar with VHDL syntax and don't have any VHDL example file. You have not provided an example file or a detailed description of the VHDL syntax for procedures and processes. I would need to search in WWW for pages and books about VHDL syntax and study them to be able to help you on finding regular expressions for the function list. As you can imagine I don't want to study VHDL syntax just for being able to help you. Please post the details about procedure and process syntax of VHDL and provide an example. Pack an example file with ZIP or RAR and upload this archive file as attachment to your next post and I will try my best to find suitable regular expressions for you.


One hint:

If you don't want to see the entire line in the function list view on which a string is found with the regular expressions defined in the wordfile, you have to use ^(...^) in UltraEdit syntax or just (...) in Perl syntax around the expression which finds the string you want to see in the function list.

For example using %[ ^t^b]+procedure[ ^t]+^(*^)$ finds lines with word procedure, but in function list only everything after word procedure (and the spaces/tabs following) up to end of line is displayed in the function list view.